To meet the demands for improved mounting densities and functionality of printed wiring boards, techniques have recently been proposed to bury each of semiconductor chips in a substrate.
As one typical example of such techniques, a package having each semiconductor chip buried in a ceramic substrate is known from the disclosure in JP H10-256429 A. The package has a BGA (ball grid array) structure in which a semiconductor chip is buried in a concavity formed in the ceramic substrate and connected to a conductive circuit formed in the ceramic substrate by the flip-chip bonding, thereby improving the heat dissipation from the semiconductor chip and allowing a narrower pitch of wiring.
However, in the above package wiring board produced by the conventional technique, wires for electrical connection of the semiconductor chip to outside are led out solely from the wiring board. So, wiring boards of this type cannot easily be stacked on each other. Even if they are stacked on each other, it is very difficult to connect the wires led out of the semiconductor chips to the stack of the wiring boards because the wiring board having the semiconductor chip buried in the substrate thereof is basically different in structure from the wiring board to be stacked on the former wiring board.
The ceramic substrate having a semiconductor chip buried therein using the conventional technique is used as a package wiring board and connected at semiconductor chip-side terminals thereof formed at a fine pitch to a printed wiring board. The led-out wire is electrically connected with a solder ball (BGA) or pin (PGA) to an external wiring board. Therefore, it has not been conceived that such wiring boards are to be stacked on each other, and the ceramic substrate is not so constructed that a plurality thereof can be stacked on each other to stack the semiconductor chips buried therein on each other.
Therefore, even if such ceramic substrates are stacked on each other, they are likely to be delaminated from each other, which causes the electrical connection and reliability of the wiring boards to be poor.
Also, techniques for producing a semiconductor module in which IC chips are stacked together are disclosed in JP H9-219490 A, JP H10-135267 A, and JP H10-163414 A, for example. These conventional techniques are intended to meet the requirement for a higher mounting density of the IC chips.
With the above conventional techniques, each IC package such as TSOP (thin small outline package), TCP (tape carrier package), BGA (ball grid array) package or the like is assembled and then a plurality of such IC packages is stacked on each other. The IC packages are connected to each other with external-connection terminals provided beforehand on each of them. These conventional techniques need many manufacturing steps, which adds to the processing costs.
Referring now to FIGS. 1 and 2, there is schematically illustrated a stack of IC packages produced by the aforementioned conventional techniques. FIG. 1 shows a stack of IC packages molded from a resin, and FIG. 2(a) is a side elevation, and FIG. 2(b) is a plan view, of a module wiring board on which the IC package stack in FIG. 1 is mounted thereon.
As shown, each of IC package 100A and 100B includes an IC mount 106, IC chip 102 mounted on the top of the IC mount 106, lead 101 for connecting the IC chip 102 and an external part to each other, and a bonding wire 103 for connecting the IC chip 102 and lead 101 to each other in a resin 104 which encapsulates a predetermined range around the IC chip 102.
The IC package 100B is piggybacked on the IC package 100A, and this stack of the 100A and 100B is mounted on a printed wiring board 105.
However, when the above IC packages 100A and 100B are piggybacked on each other in the direction of their thickness and the stack is mounted on the printed wiring board 105, the thickness of the resin 104 will increase total module thickness.
Also, when each of the IC packages 100A and 100B is mounted horizontally on the printed wiring board 105, the semiconductor module as a whole will be larger in size.
Further, since the IC packages 100A and 100B, upper and lower in relation to each other, are connected with the leads 101 to the printed wiring board 105, respectively, if they are stacked on each other with a misalignment or misregistration, a short-circuit is likely to take place between the leads 101.
Thus, the application of the aforementioned conventional techniques to the IC packages used in electronic devices required to be smaller in size such as IC cards, mobile telephones, etc. cannot be a solution to the problems of mounting density and low profile of the IC package.
Accordingly, the present invention has an object to overcome the above-mentioned drawbacks of the prior art by providing a semiconductor chip mounting wiring board which can positively be connected to the semiconductor chips and in which wires led out from the semiconductor chips can further be stacked.
The present invention has another object to provide a method of producing a semiconductor chip mounting wiring board whose connection is highly reliable.
The present invention has still another object to provide a semiconductor module made by stacking wiring boards each having a semiconductor chip mounted thereon and interlayer members alternately on each other and applying hot-pressing to them, and which has a high connection reliability and can be designed for a higher mounting density and lower profile.
To attain the above objects, the inventors of the present invention found, through many experiments, the fact that by stacking wiring boards each having a semiconductor chip mounted beforehand on a wiring board and interlayer members each having an opening to receive the semiconductor chip alternately on each other with an adhesive layer applied between them, applying hot-pressing to the thus formed stack, instead of molding semiconductor chips in a resin as in the prior art, to bury the semiconductor chip in the opening in the interlayer member, and electrically connecting the semiconductor chips to each other via a viahole or conductor post formed in the interlayer member, the distance between the semiconductor chips can be reduced and troubles caused by wire resistance and inductance can be minimized so that electric information can be transmitted at a high speed without any delay, and the mounting density, functionality and profile of the printed wiring board can be improved.